Static RAM is a high-performance memory extensively applied to the encrypted circuit; however, as the circuit power consumption is related to the data as read, it may be probably decoded by the differential power analysis. Output circuit of existing static RAM is single-terminal output; dual-rail pre-charge logic is not applicable to the design of static RAM due to the lack of fully identical complementary output; on the contrary, three-phase dual-rail pre-charge logic and self-timing three-phase dual-rail pre-charge logic can realize one-off charging/discharging for major nodes in each periodic circuit through addition of discharging process on SABL basis, which can overcome the disadvantage of power consumption difference incurred by inconsistent load and wiring capacitance; nevertheless, as they are requested to reset the output before the end of each cycle, it is impossible to keep the data as read; therefore, they are not applicable to the design of static RAM for defense of power attack.